1. Field of the Invention
The present invention relates to a voltage-current converter and a voltage controlled oscillator.
2. Description of Related Art
In recent years, the threshold value voltage of a transistor has been decreasing along with the high-speed operation and reduced voltage of LSI. Along with this, a leak current flowing between a source and a drain even when the transistor is in an off state, which is off leak, cannot be ignored. The off-leak current tends to be increased when the threshold value voltage of the transistor is low and the temperature is high. The off-leak current greatly influences on each characteristic especially in an analog design; therefore, any proper countermeasure should be taken in a low-voltage operation area.
An off-leak current cancel circuit for canceling such off-leak current is disclosed in Japanese Unexamined Patent Application Publication No. 2002-344251 (Kondo). The off-leak current cancel circuit disclosed in Kondo will be described with reference to FIG. 4. The off-leak current cancel circuit includes cancel portions 110 and 120. The cancel portions 110 and 120 cancel off-leak current of an input circuit protecting PMOS 102 and NMOS 103. The cancel portions 110 and 120 are formed on a semiconductor substrate of the PMOS 102 and NMOS 103. The PMOS 102 is connected between the input terminal 101 and a power supply potential VDD. The NMOS 103 is connected between the input terminal 101 and a ground potential GND.
The cancel portion 110 cancels off-leak current of the PMOS 102 and includes a PMOS 111 and NMOS 112, 113, 114. The PMOS 111 has a gate length identical to the PMOS 102 and a gate width of 1/n of the gate width of the PMOS 102. The PMOS 111 has a source and a gate connected to the power supply potential VDD and a drain connected to a node 131. That is, the PMOS 111 is diode-connected in the reverse direction like the PMOS 102 and configured so that 1/n of the off-leak current flowing in the PMOS 102 flows.
The node 131 is connected to the drain and the gate of the NMOS 112 whose source is connected to the ground potential GND. The node 131 is connected to the gate of the NMOS 113 whose drain and source are connected to the input terminal 101 and the ground terminal GND, respectively. The NMOS 113 has a gate length identical to the NMOS 112, and a gate width which is n times as large as the gate width of the NMOS 112. That is, the NMOS 112 and 113 constitute a current mirror circuit and the current n times as large as the current flowing in the NMOS 112 flows in the NMOS 113.
The NMOS 114 has a drain connected to the node 131. The NMOS 114 has a source connected to the ground potential GND and a gate connected to the power supply potential VDD. Accordingly, the NMOS 114 is always in on state. The NMOS 114 has a gate length and gate width formed so that the ON resistance of the NMOS 114 exhibits quite a high resistance value. Accordingly, the NMOS 114 makes the node 131 the ground potential GND for stability of the operation when almost no off-leak current is present in the PMOS 111.
The cancel portion 120 cancels off-leak current of the NMOS 103 and includes an NMOS 121 and PMOS 122, 123, 124. The NMOS 121 has a gate length identical to the NMOS 103 and a gate width of 1/n of the gate width of the NMOS 103. The NMOS 121 has a source and a gate connected to the ground potential GND and a drain connected to a node 132. That is, the NMOS 121 is diode-connected in the reverse direction like the NMOS 103 and configured so that 1/n of the off-leak current flowing in the NMOS 103 flows.
The node 132 is connected to the drain and the gate of the PMOS 122 whose source is connected to the power supply potential VDD. The node 132 is connected to the gate of the PMOS 123 whose drain and source are connected to the input terminal 101 and to the power supply potential VDD, respectively. The PMOS 123 has a gate length identical to the PMOS 122, and a gate width which is n times as large as the gate width of the PMOS 112. That is, the PMOS 122 and 123 constitute a current mirror circuit and the current n times as large as the current flowing in the PMOS 122 flows in the PMOS 123.
The PMOS 124 has a drain connected to the node 132. The PMOS 124 has a source connected to the power supply potential VDD and a gate connected to the ground potential GND. Accordingly, the PMOS 124 is always in on state. The PMOS 124 has a gate length and gate width formed so that the ON resistance of the PMOS 124 exhibits quite a high resistance value. Accordingly, the PMOS 124 makes the node 132 the power supply potential VDD for stability of the operation when almost no off-leak current is present in the NMOS 121.
Next, explanation will be given on operation. For example, when the ambient temperature is a room temperature and there is almost no off-leak current, the NMOS 114 of the cancel portion 110 is in an ON state and accordingly, the node 131 is almost ground potential GND and the NMOS 112 and 113 are in an OFF state. Similarly, the PMOS 124 of the cancel portion 120 is in an ON state and accordingly, the node 132 becomes almost power supply potential VDD and PMOS 122 and 123 become OFF.
Here, it is assumed that the ambient temperature has increased and off-leak current flows in the PMOS 102. The PMOS 102 and the PMOS 111 in the cancel portion 110 are formed on the same semiconductor substrate and have an identical gate length. Accordingly, off-leak current also flows in this PMOS 111. When the gate length is identical, the off-leak current flowing is proportional to the gate width and accordingly, the off-leak current flowing in the PMOS 111 becomes 1/n of the PMOS 102. The off-leak current flowing in the PMOS 111 flows into the node 131. The node 131 is connected to the NMOS 112 and 114 but since the NMOS 114 has quite a high resistance, almost no current flows in the NMOS 114. Accordingly, in the NMOS 112, current almost identical to the PMOS 111 flows. The NMOS 112 is connected to the NMOS 113 constituting a current mirror circuit of the current ratio of n multiples. Thus, current n times as large as the PMOS 111 flows in the ground potential GND through the NMOS 113. The current of the PMOS 111 becomes 1/n of the current of the PMOS 102; therefore, the current identical to the current flowing in the PMOS 102 flows in the NMOS 113.
Thus, the off-leak current flowing in the PMOS 102 all flows into the ground potential GND via the NMOS 113 and no off-leak current flows into the signal source connected to the input terminal 101. Similarly, the off-leak current flowing in the NMOS 103 is detected by the NMOS 121 for monitoring of the cancel portion 120 and supplied from the power supply potential VDD via the PMOS 123 to the NMOS 103. Accordingly, no off-leak current flows to the signal source connected to the input terminal 101.
As has been described, the circuit shown in FIG. 4 is a circuit for canceling the off-leak current of the input circuit protecting PMOS 102 and NMOS 103. The off-leak current flowing in the NMOS 103 is detected by the NMOS 121 for monitoring of the cancel portion 120. The current is supplied from the power supply potential VDD via the PMOS 123 to the NMOS 103 to cancel the off-leak current. Based on this background art, when the cancel circuit described above is applied to the voltage-current converter, the problem is raised as follows.
FIG. 5 is a circuit diagram showing a configuration of the voltage-current converter. In the voltage-current converter, the off-leak current of the NMOS 4 is cancelled by a second current generating circuit 12. Thus, the second current generating circuit 12 has a function of decreasing the off-leak current.
Even when the voltage of the input terminal 1 is the ground potential GND, current flows in the PMOS 6 due to the off-leak current of the NMOS 4. This off-leak current greatly depends on the threshold value voltage and the temperature. For example, the off-leak current especially increases when the threshold value voltage of the transistor is low and the temperature is high. Therefore, the off-leak current cannot be ignored depending on the diffusion state in the LSI and the operating temperature of the LSI or the like. Therefore, it becomes difficult to generate the current according to the input voltage. As such, the off-leak current degrades the accuracy of the output current, which degrades the characteristic of the analog circuit.
When the potential of the input terminal 1 increases and the gate potential of the NMOS 4 exceeds the threshold value voltage, current flowing in the node 21 also increases in proportion to the voltage amount that exceeds the threshold value voltage. However, when the large volume of off-leak current flows in the NMOS 4, it becomes difficult to generate the current according to the input voltage. The gate, the source, and the bulk of the NMOS 8 of the second current generating circuit 12 are connected to the ground GND. Therefore, even when the off leak flows in the NMOS 8, there is no voltage fluctuation occurred between the gate and the source. Further, there is no potential difference between the source and the bulk. Therefore, there is no change in the threshold value voltage of the transistor due to the back gate effect and the voltage fluctuation between the gate and the source. However, in the NMOS 4 of the voltage-current converter 11, the gate is connected to the input terminal 1, the source is connected to the resistance element 3, and the bulk is connected to the ground GND. Therefore, there is generated a difference potential between the source and the bulk, whereby the threshold value is made somewhat high due to the back bias effect. The off-leak current flowing in the NMOS 4 depends on the threshold value and the voltage between the gate and the source. The off-leak current flowing in the NMOS 4 of the voltage-current converter 11 is different from the current amount generated in the NMOS 8 in the second current generating circuit 12. Therefore, the current value almost the same as the current value flowing in the NMOS 4 cannot be generated in the NMOS 8. Accordingly, it is not possible to cancel the off-leak current flowing in the NMOS 4 without fail.